1. Field of the Invention
The present invention relates to an aperture array and a charged particle lithography system using an aperture array.
2. Description of the Related Art
In the charged particle lithography field, various aperture pattern schemes for a multi-beam pattern definition device are known. For example, U.S. Pat. No. 5,369,282 to Arai discloses an electron-beam lithography system using a blanking aperture array (BAA) as the pattern definition device. The BAA has a number of rows of apertures, and the images of the apertures are scanned over a stripe of the substrate in a controlled, continuous motion.
Arai teaches to group aperture rows of the BAA by exposure order. The substrate stripe is first exposed using a full dosage, as delivered by a first group, and then subsequently exposed to compensate for proximity effects exhibited by the substrate stripe, as delivered by a second group. In some embodiments, corresponding apertures of the first and second groups are offset from each other in relation to an electron scanning direction and/or to a mechanical scanning direction. Further, within each group, apertures on every other row align in the electron-scan direction and all rows align in the mechanical-scan direction.
U.S. Patent Application No. 2011-0073782 to Wieland discloses an electron-beam lithography system with a beamlet blanker array with apertures for generating 16 sub-beams arranged in a square 4×4 array, where each sub-beam is divided into 9 beamlets arranged in a square 3×3 array. Wieland teaches various writing strategies using such beamlet arrangements to achieve exposure of a wafer surface when the wafer is moved with respect to the beamlet blanker array and the beamlets are deflected over the surface of the wafer.
Among other deficiencies, the system of Arai lacks sufficient throughput for commercial viability and neither system provides an optimum arrangement of sub-beams or beamlets for uniform exposure of the wafer. Thus there is a need for alternative aperture pattern schemes that improve throughput and distribution of the writing beams on the wafer surface.